A significant trend in semiconductor manufacture is the steady increase in the number of elements that are included on a single chip. This has involved making the individual elements smaller and packing them closer to increase the density. With the increase in packing density, there has grown the need for isolation barriers between elements. Typically these isolation barriers take the form of guard rings or chanstops, which are regions of relatively high doping, to reduce leakage between neighboring elements, as might be caused by spurious inversion of the regions between active elements. Such inversions are apt to occur because of the voltages on the conductive runners overlying the chip used for applying operating voltages to the active elements. These chanstops advantageously are usually formed underneath a field oxide, which is a relatively thick oxide used to overlie the chip at passive regions between the active elements.
In complementary integrated circuits, there will be instances where contiguous transistors in the chip are of the same conductivity type in which case a single chanstop will generally be sufficient for isolation and instances where contiguous transistors are of opposite conductivity type in which case a chanstop of each type is usually desirable for optimum isolation. For saving space it is usually advantageous that this pair of complementary chanstops be back-to-back and it will be convenient to refer to such a structure as a twin chanstop.
One consideration which is pervasive in the manufacture of integrated circuit devices, particularly in high densities, is a fabrication process which results in low cost. Typically this requires a process which permits high yields, which end in turn is best served by a process which includes few critical steps, particularly masking steps requiring accurate registration.
One characteristic of a process in accordance with the present invention is that by the addition of a single masking step beyond those normally required there can be provided, where desired, single chanstops of either type or twin chanstops, self-aligned under the field oxide.
Another consideration which can be important for CMOS devices which employ chanstops is the need to maintain at a relatively high value the breakdown voltage of the junction formed between the chanstop and other regions of the chip including a chanstop of the opposite type.
The present invention takes account of this consideration also.